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Inter-Integrated Circuit
9.3
9.3.1
Register definitions
I 2 C memory map
The I 2 C has ten eight-bit registers. The base address of the module is hardware programmable. The I 2 C
register map is fixed and begins at the module’s base address. The following table summarizes the I 2 C
module’s address space. The following section describes the bit-level arrangement and functionality of
each register.
Table 9-1. I 2 C memory map
Address
Base + 0x0000
Register
I 2 C Address Register 1 (IICA1)
Access
Read/Write
Reset
0x00
Details
Base + 0x0001
Base + 0x0002
Base + 0x0003
I 2 C
I 2 C
I 2 C
Frequency Divider Register (IICF)
Control Register 1 (IICC1)
Status Register (IICS)
Read/Write
Read/Write
Read
0x00
0x00
0x80
Base + 0x0004
I 2 C Data IO Register (IICD)
Read/Write
0x00
Base + 0x0005
Base + 0x0006
I 2 C
I 2 C
Control Register 2 (IICC2)
input programmable filter (IICFLT)
Read/Write
Read/Write
0x00
0x00
This section consists of the I 2 C register descriptions in address order.
Refer to the direct-page register summary in the “Memory Maps” on page 45 for the absolute address
assignments for all I 2 C registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
156
Freescale Semiconductor, Inc.
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